1. Field of the Invention
The present invention relates to electronic memory circuits and in particular to a memory circuit with an optical input.
2. Description of the Related Art
Electronic memory circuits for storing information and data in a binary form are subject to constant and rapid technological progress. On the one hand, their capacities, i.e. the amount of information that can be stored, are being increased more and more. On the other hand, these memory circuits designed as semiconductor components become increasingly fast, i.e. the time required for a writing operation or a reading operation is becoming increasingly short, and/or the number of the elementary writing operations and/or reading operations per time unit is increasing. Here a limit has been reached which is formed by the physically possible range of electric transmission of addressing signals, control signals and data signals.
With an increasing frequency of the signals transmitted to and from a memory circuit, the problems encountered in electrical connections due to parasitic inductances and capacitances as well as due to a cross-talk between adjacent lines increase, whereby signal qualities deteriorate. In addition, each change in the impedance along a signal path causes disturbances in the form of reflections. Each end of a conductor line, each solder contact, each pin-and-socket connection and each wire bond connection may cause, in this manner, disturbing reflections which cause a significant deterioration of the quality of the signals transmitted. In practice, numerous transitions in the form of solder contacts or pin-and-socket contacts occur between a semiconductor chip, a circuit board, a plug-in module and another semiconductor chip.
A deterioration of a signal quality may be compensated, within certain limits, by expensive circuits at the end of a line degrading the signal quality, i.e. at the input area of a circuit receiving the signals, whereby, however, significant cost due to a consumption of further chip space as well as other disadvantages, such as an increased energy consumption, are created.
Special problems with regard to the signal quality arise in testing semiconductor memory circuits during manufacturing. To recognize faulty memory circuits and to remove them from the manufacturing process as early on as possible, they are temporarily contacted by means of testing needles and checked for their function by means of a testing device immediately after their production, while they are still on the entire semiconductor wafer, i.e. before being diced. However, these testing needles have a finite bandwidth which is not sufficient to test modern memory circuits with the signal frequency and the data throughput to which they will be exposed as a finished memory component, for example in a computer. Therefore such a test of a memory component on a wafer can only have limited validity. As a consequence, faulty memory circuits on a wafer are not recognized as such and discarded from the manufacturing process, but are housed, contacted and retested in further costly process steps. In this manner, considerable manufacturing costs arise for memory components which are not functional and therefore cannot be sold, but must be destroyed. These costs must be apportioned to the fault-free components to be sold, whereby they become considerably more expensive.
In addition, all electrical lines, for example on a mother board, a memory socket, a memory module etc., represent antennas which, on the one hand, send out potential spurious signals for other electrical lines and circuits, and, on the other hand, receive spurious signals of other electrical lines or circuits and supply same to the circuits connected. This problem takes on considerable proportions since there is a tendency, for various reasons, to concentrate an increasing number of lines, which transmit signals clocked at an increasing speed, to a decreasing amount of space.
A further problem is an influence on the signal quality by disturbances of a supply voltage, inevitable in practice, which influence, for example, the signal edges and/or their steepness (ground bounce, Vcc drops, etc.).
A further problem arises in a run length adjustment, which leads to additional parasitic capacitances and inductances in the case of an electrical realization.
Each open electrical contact of a semiconductor circuit further presents the risk of a destruction of the semiconductor circuit by an electrostatic discharge (ESD), whereby a semiconductor circuit may be irreparably damaged with each manipulation, in particular when it is inserted into or removed from a circuit board and/or a socket.
Generally, it can be established that each electrical connection in the form of a conductor line, a solder, plug-in or wire bonding connection causes manufacturing expense and thus raises the price of the respective final product and further represents a potential source of trouble in the production and operation.